Abstract
Abstract(英文摘要) As technology advances, the process gradually updates, more and more circuits can be design in the same area, and the performance is getting better and better. With this scientific and technological progress, many people are willing to try to carry out large-scale system integrated in one chip design, but if they want to put the signal into a computer for analysis and processing, they must use the analog to digital converter. So analog to digital converter is the essential bridge between nature world and digital world. Due to the rapid development of medical technology, the requirement of the physiological signal measurement promote gradually. In this thesis, a sampling frequency of 10MHz, the signal bandwidth of 20kHz, and oversampling ratio (OSR) for 256 of the second-order delta-sigma analog-to digital converters, mainly used in biomedical sensing. The discrete-time system of Delta Sigma analog to digital converter is implemented by switch capacitor circuit. The affect by the clock jitter and additional delay (Excess Loop Delay) is small, but the gain bandwidth requirement of the amplifier is higher. So the high-resolution system can be designed for the low-speed application. The whole architecture includes amplifiers, comparator, analog switches ...... and so on. Add many kinds of non-ideal effects into the system to simulate like Clock Feedthrough, Clock Jitter, Finite Gain, Limited Gain bandwidth Product, Thermal noise...... and so on to formulate the amplifier specification. And then the choice of this work, Full Feed -forward low distortion structure, significantly reduces overall system amplifier specifications and the distortion of the integrator overload. This paper uses a standard TSMC 0.18um CMOS process design, and Cadence Spectre software for circuit simulation. Finally the technique of Full- Customer design implement the whole circuit. The circuit operating voltage at 1.8V, signal bandwidth 20kHz, signal to noise ratio SNR> 95dB, effective number of bits reach more than 15bits, the overall average power consumption is 3.06mW, the figure of merit (FoM) is 1.06 pJ/conv. and the total Layout area is 0.7x0.67〖 mm〗^2