Abstract
Analog to digital converter are the essential bridge between nature world and digital world, and this thesis introduces a successive approximation analog to digital converter mainly used in the radar receiver, where the received RF signals are frequency-reduced after high-speed sampling, and then amplified by the baseband amplifier. The signals are then processed by the analog to digital converter and finally the converted digital signal to the computer for data analysis. In the thesis, we have proposed a successive approximation analog to digital converter, which has been greatly improved the capacitance matrix, making the size 50% less than traditional ones. The ADCs with monotonic structure capacitance matrix of different places are able to maintain the common-mode voltage, which is a huge benefit to avoid comparator from generating random offset voltages. The 10 bits in 20 million samples per second successive approximation analog to digital converter is implemented in a TSMC 65 nm CMOS process. The design is operated in 1V with ENOB 9.97 and perfect DNL, INL. The average power consumption is 620μW, and the average energy consumption is 30fJ each conversion.