Abstract
AbstractIn this thesis, the proposed simultaneous forward and inverse discrete cosine transform (DCT) core exploits sorting and butterfly method that can be cost-efficient implemented. In real-time video encoder, the forward and inverse transforms are needed to be executed simultaneously. The proposed architecture has three advantages: First, multi-function work in DCT/IDCT can be simultaneously computed. Second, it can support real-time system in video encoder. Third, it exploits sorting and butterfly method by only one 1-D core and a transpose memory (TM), which can simultaneously compute two types of DCT and IDCT. Supporting MPEG-1/2/4 standards in video format as well as IEEE IDCT standard precision, the proposed design is implemented in a TSMC 0.18-um 1P6M CMOS technology. Measurement results show clock rate of 200M/sec while operated in simultaneous forward and inverse DCT mode and resultant circuit includes 19.65K logic gates with maximum throughput rate of 400Mpixel/sec. The proposed architecture can support HDTV video (1920×1080P@60 HZ) requirement operated in real-time video encoder.