Abstract
We design a RISC-based DSP core. We focus on performance and code density. We use VLIW and SIMD techniques in our design to provide higher computation power. Moreover, we combine some instructions into a compound instruction to improve code density. We have implemented the DSP core in synthesizable RTL Verilog. The core is able to run at 120 MHz when targeted towards a TSMC 0.35 um cell library.