Abstract
A Static Random Access Memory (SRAM) measurement unit is presented to sample the voltage signals of bit line pairs and to amplify the weak signal to higher voltage differential level. According to the measured result, the reliability analysis can be easily completed through curve fitting process. The proposed circuit is designed and simulated with a 1K-bit SRAM by using the UMC 0.18μm 1P6M CMOS process. The analyzed result can provide designers to verify/strengthen their memory circuit design.