Abstract
During the initial design stage, in addition to the consideration of functions, the thermal performance of three dimensional MultiChip Module-Vertical (MCM-V) is one of the main objectives. It needs to be tested through by various simulations and experiments which would both take much time and cost much money. Consequently, the principal purpose of this study is to find out an efficient way to improve the thermal performance of the three-dimensional MCM-V to extend the expiration time of the package.This work is first to establish a three-dimensional finite element heat transfer analysis model for MCM-V package by the application of the finite element analysis software package ANSYSR. There are two ways to define the required convective and radiative boundary conditions for thermal analysis of the package (including the Printed Circuit Board) : 1) the surface temperature distribution of package and PCB measured by IR Thermography under natural convection environment and 2) based on the convection/radiation correlation models developed by Ellison (1989) and Ridsdale et al. (1994). In contrast with the temperature measurement of the functional diode on the thermal chip, this work demonstrates the applicability and validity of the three-dimensional finite element heat transfer analysis model of MCM-V package.Moreover, the chip temperature measured usually depends on the allocation of the diode. To explore such an effect, this work also measures the surface temperature of the specified portion of the package by micro-lens of IR thermography to modify the thermal boundary conditions. Hence, the three-dimensional finite element model of MCM-V can achieve more accurate results.Finally, the three-dimensional finite element model established for thermal analysis is extended to the parameter studies for MCM-V package on the effects of chip junction temperature and thermal resistance. The parameters studied include thermal conductivity coefficients of materials, thermal vias, copper spreader, operating power, chip size, chip stacked layers and chip stacked type etc. The results of the research are of great worth for electronic packaging industry during the initial design stage of MCM-V package.