Abstract
Through-Silicon Via (TSV) is a promising technology to reduce the length of interconnect in a three dimensional integrated circuit (3D-IC). However, the area overhead of TSV also poses a negative impact on a 3D-IC. Using too many TSVs will increase the die size and cancel out the benefit brought by TSV. Therefore, in this paper we will minimize wire length taking into account the number of TSVs and their size during placement in 3D-IC. Since the number of TSVs is determined by placement, a minimum cost cut algorithm is proposed in this thesis. The experimental result shows the comparisons in different algorithms. The best algorithm is minimum cost cut partitioning placement algorithm. Most of all, the runtime is the fastest, too.