Abstract
Multiple Power Domain (MPD) is a technique to optimize power and speed by providing multiple supply voltages to modules. Although there are many research on MPD in 2D IC, less research pay attention to MPD in 3D IC. In Lin’s thesis, an algorithm was applied to MPD in 3D IC to take into account issues such as 3D floorplan, IR drop, temperature, area, etc. based on an integrated architecture of stacked-TSV (Through-Silicon-Via) and power distributed network (STDN-Stacked TSV Distributed Network) proposed by Chen. In this thesis, we propose a post-floorplanning power optimization algorithm to further reduce power given a floorplan of MPD design produced by Lin’s algorithm. Experimental result show that our algorithm achieves more power reduction, less area of footprint and less total wirelength of signal interconnections.