Abstract
The reliability of through-silicon via (TSV) is becoming increasingly important in 3D ICs. Since the higher failure rate of TSV in clock tree yields more bad chips. Accordingly, the previous work proposes a novel TSV fault-tolerant unit (TFU), which can provide tolerance against TSV failure in a 3D clock network. However, the TFU structure’s additional buffers could take considerable power consumption. Also, the TFU structure In this thesis, we present two methodologies to resolve the TFU delay buffer overhead. (1) Analyze clock signal delay and resize the TFU’s delay buffers by linear programming. (2) Insert crosslink in TFU to achieve further buffer sizing and provide variation tolerance. Experimental results demonstrate that our methodologies make the circuit have lower power consumption and better variation tolerance compared with the previous work.