Abstract
AbstractFlip chip has distinguishing characteristics of light weight, thin, and small dimensions. This type of package has brought about broad study of electronic industrial because of its good thermal property and high I/O density. CTE mismatch between silicon and BT board is so colossal that flip chip need filling underfill to keep the long-term reliability. Moreover, underfill is usually thermosetting polymer and the process of hardening is time-consuming. If the die is found it cannot work after baking of underfill, the die cannot be replaced. For avoiding the disadvantage of filling the underfill and keeping good reliability, this research proposes a novel concept of no underfill with constraint layer flip chip package. This novel flip chip package is bonded a constraint layer with similar CTE of die on the bottom of BT board, and furthermore the CTE mismatch can be diminished and the package can obtain available reliability. In this research, the 2D model will be constructed to do parametric studies. Moreover, whether the cutting and opening hole of constraint layer can enhance the reliability will be discussed.When discussing the cutting and opening hole of constraint layer, the 3D finite element model is necessary. Due to the calculation is so huge, the equivalent beam theory is applied in this study. The 3D ball of this study will be replaced by equivalent beam that possesses similar force-displacement relationship of 3D ball and the CUP time will be decreased and simultaneously we can obtain reasonable solution. This paper provides another methodology for analyzing thermal stress/strain of electronic package.