Abstract
In recent years, the improvement of the semiconductor technology have been focused on how to effectively use the costly chip area. To accommodate more transistors in a single chip, people try to minimize the size of the transistors for the past few decades. As the channel length minimize to less than ten’s of nano-meter regime, the characteristic of the MOSFET can not be easily controlled. New ways to increase circuit complexity without large chip size are in great demand. One way of doing so is by stacking the semiconductor chips. That is the main idea of the three-dimensional integrated circuit(3DIC). The key of realizing 3DIC is development of “through silicon via”(TSV). TSVs’ are generally composed of long and wide copper lines. This through substrate wires might induced large potential fluctuation in the substrates, leading to much greater substrate noises. In this study, we intend to investigate these additional substrate noise as a results of the TSVs’. First, the problems of the TSVcoupled noise are outlined. We then discuss the distribution & magnitude of the TSV-coupled under different condition noise using the simulation software. The simulation results help us conclude some general guidelines of designing the TSV layout, guard-ring structures, so that, the chip area can be effective utilized.