Abstract
In modern wireless communication systems, frequency synthesizers with high frequency resolution are used to up/downconvert signals to desired bands precisely. Phase-locked loops (PLLs) with the delta-sigma technique are a common way to achieve high frequency resolution. However, quantization noise is inevitable introduced during division ratio dithering, it greatly degrades the out-band noise performance especially in a high-bandwidth phase-locked loop. We focus on the study of quantization noise suppression. Analysis of quantization noise from delta-sigma modulation and the interface between continuous-time and discrete-time signal processing in PLLs plays an important role in this thesis. Based on this analysis, we propose a high oversampling rate (H-OSR) delta-sigma frequency synthesizer on which an finite-impulse response (FIR) digital filter and a novel half-integer frequency based on the phase compensation technique are embedded. The simulation result shows that the proposed architecture is able to suppress the quantization noise by 21 dB compared with the conventional MASH 1-1-1 structure. Moreover, the notch filtering effect from the FIR filter can further reduce quantization noise at the specific frequency, and improve the phase jitter performance. The proposed frequency synthesizer was verified by the silicon results in a TSMC 0.18μm CMOS process. Output frequency range is from 2.58 GHz to 3.45 GHz, the core power consumption is 12 mW. At the frequency of 1/5 and 3/5 reference frequency in the phase noise spectrum, the notch filtering effect can be found. Besides, FPGA is used to implement the delta-sigma modulator and the FIR filter during the measurement.