Abstract
Multiply-And-Accumulate (MAC) is the most frequently used operation in many DSP applications. We propose a software method that can generate high-performance MAC units in synthesizable HDL format. Our tool integrates several novel techniques including a modified radix-4 Booth encoding, a three dimensional Wallace tree, a sign-extension prevention scheme, and a hybrid carry-select/carry-look-ahead adder. It allows users to specify the number of bits in both inputs and output, the number system (signed or unsigned or decided by command inputs), the number of pipeline stages, saturation option on overflow, accumulator type (“addition only” or “addition and subtraction”), and pipeline stall as well as accumulator initialization capability. A typical MAC unit (16x16 inputs, 40-bit Accumulation, 2-stage pipeline) can be generated within seconds and run at over 280 MHz in post-layout simulation typical case when targeted toward a TSMC 0.35μm CMOS cell library.