Abstract
In this thesis, we propose a technology mapping algorithmfor CPLD architectures. Our algorithm proceeds in two phases:mapping for single-output PLAs and packing for multiple-output PLAs.In the mapping phase, based on the results in [4],we propose a Look-Up-Table (LUT) based mapping algorithm.We will take advantage of existing LUT mappingalgorithms for area and depth minimization.We also study, for a given (i, p, o)-PLAblock structure, the problem of selecting the values of input and productterm constraints for mapping for single-output PLA.Benchmark results show that our algorithm producebetter results in terms of area and depth as compared to those by TEMPLA.