Abstract
To further scale down equivalent oxide thickness (EOT) and get good electrical properties, a high quality Ge oxide interfacial layer (IL) is one of the key challenges for Ge MOS devices. A GeO2 formed by H2O plasma deposition in an ALD is used as a main IL in this thesis. Different processes are studied for Ge MOS devices, which includes post deposition annealing (PDA), different IL growth temperature, and in-situ nitrogen treatment. The best conditions are implemented on Ge MOSFETs fabrication. The PDA is performed by a rapid thermal oxidation (RTO), which can passivate oxygen vacancy and provide better reliability. A Ge MOS device with 0.9 nm EOT and low leakage current of 10-3 A/cm2 is present. Although the EOT has slightly increased, the RTO sample shows good electrical properties such as low interface trap density (Dit) and good reliability. It is found that EOT is quite different compared to the previous work. Some methods are provided to find the problems. The first way is changing the physical thickness of high-k dielectric layer. It found that it is difficult to crystallize high-k dielectrics and the k value of interfacial layer is quite low. Use the post metal deposition annealing can enhance the crystallization and enhance the intermixing between high-k and interfacial layer. As a result, 0.48 nm EOT and 10-1 A/cm2 leakage current is achieved. At the same time, hysteresis and reliability are improved as well. The results can be confirmed by TEM images. Growth temperature is modified to obtain the best interfacial layer properties. The higher (370oC) and lower (150oC) growth temperature exhibit larger flat band voltage and hysteresis. These properties show that there are more traps in high-k dielectrics, leading to serious reliability degradation. The 250oC growth temperature shows 0.48 nm EOT, and it is the best condition for interface layer growth. On the other hand, in-situ nitrogen treatments in interfacial layer have been used. In-situ nitrogen treatment can suppress Dit but increase EOT and some traps in high-k dielectrics. Hydrogen treatment can enhance the quality of high-k but increase some traps in interfacial layer. Both treatments have their own advantages. The work in the next chapter will attempt to combine these two in-situ treatments. At last, Ge MOSFETs are fabricated with the best condition from previous works. The hydrogen treatment can provide better gate control characteristic and increase Gm as well. The nitrogen treatment can suppress off current and S.S. To obtain all advantages, these two treatments have been combined with Ge MOSFETs processes. As a result, the high Gm value of 3559 μA/V and low S.S. of 238 mV/dec are achieved. The peak hole mobility is 401 cm2/V-s with 0.47 nm EOT. The in-situ nitrogen treatment together with hydrogen treatment in interfacial layers is a promising approach for Ge MOSFET devices.