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以0.18μm單層多晶矽CMOS製程開發之懸浮閘電晶體與其寫入準確率修正
Thesis

以0.18μm單層多晶矽CMOS製程開發之懸浮閘電晶體與其寫入準確率修正

林柏丞
Masters, 國立清華大學, 電機工程學系
2015

Abstract

懸浮閘電晶體 單層多晶矽懸浮閘電晶體 Floating Gate MOSFET Single Poly FGMOS
In order to save various kinds of signals, floating gate device is widely used as nonvolatile memories, such as EPROM, Flash memory and so on. Because floating gate device is compatible with strandard CMOS process, there are many researches about applying floating gate device to system on chip. But as process moves into deep-submicron process, there will be many difficulties to achieve floating gate device. This study proposes a floating gate device with its characteristics which is manufactured by TSMC 0.18μm CMOS 1P6M single poly process. Proposed floating gate device is constructed with two P-channel MOSFETs and a MOS varactor. This device is programmed by impact ionization hot electron injection, and erased by FN tunneling. We tested this device with many different combinations of biases, then compared the result of programming, erasing, device endurance, and data retention characteristics is given in this study. With those device characteristics, by using a basic circuit which can measure the voltage of floating gate, the reasons that influence on the programming accuracy are proposed in this study. Then a solution is proposed to increase the programming accuracy, which is verified by measurement results. Finally, possible improvements of this floating gate device are discussed.

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