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以WAT參數資料建構半導體研發設計階段黃金晶方群聚分析
Thesis

以WAT參數資料建構半導體研發設計階段黃金晶方群聚分析

游淑敏
Masters, 國立清華大學, 工業工程與工程管理學系
2007

Abstract

黃金晶方 晶圓允收測試 製程空間 主成份分析 自我組織映射網路 Golden Die Wafer Acceptance Test Process Window Principal Component Analysis Self-Organizing Map
Taiwan's semiconductor industry has played a prominent role in global semiconductor market because of its excellent and outstanding achievements. The new challenge to Taiwan's semiconductor industry is how to maintain the competitive advantages and create a whole new business market. In the semiconductor research and design (R&D) stage, the R&D department would find the golden die that meets simulation performance of circuit design. The analysis of process window can be accelerated by the feedback of wafer acceptance test (WAT) data of the golden die. However, it is difficult to define and select the golden die due to cost restrictions and limited time. Accordingly, this research aims to build a model to analyze WAT data at R&D stage during semiconductor fabrification to help R&D department resolve these problems. In this research, WAT data are collected and utilized to classify dices on a wafer and find similar golden dice based on the pre-defined golden die. Similar golden dices provide much more feedback of WAT data, and then the efficiency of process window analysis can then be improved. Real WAT data at R&D stage during semiconductor fabrification are collected from a famous semiconductor manufacturing company and were experimented through the presented analysis model. The experimental results show that the presented model can successfully find similar golden dice in the cluster that a golden die falls. Therefore, the proposed methodology can help the R&D department analyze process window more quickly and efficiently, and the analysis time and cost are greatly reduced at R&D stage during semiconductor fabrification.

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