Abstract
Continuous-time ΣΔ modulators are popularly used in SOC due to its low power consumption and anti-aliasing filter-embedded signal transfer function. However, the quntizers’ resolution which is limited by hardware cost and extra time delay of dynamic element matching circuit. To further increase modulators resolution, higher OSR was used in conventional designs which led to high power consumption of the whole system. In the proposed CTDSM, we construct an output-truncated SAR which has first-order noise-shaping as the quantizer in the CTDSM. The CTDSM consists of a 3rd loop filter, a 6 bits SAR ADC, a 3-bit current-steering DAC and a 3-bit DEM circuit. The 3-bit output truncated doesn’t degrade the modulator’s performance much due to the first order noise-shaping. Since the DEM function in our new arrangement is not in series of loop operation, DEM circuit with longer time delay but small area could be used. In the meanwhile, the DEM’s number of bits decrease from 6 to 3. The noise-shaped mechanism is realized by the capacitor DAC in SAR and consumes small area. This work was realized in TSMC 90nm general purpose CMOS process. The modulators bandwidth is 1.92MHz with clock rate of 61.44MHz. The measurement result shows it achieves 72.2dB SNDR with 0.8Vpp,diff input signal. The CTDSM power consumption is 2.92mW, resulting in FOM of 229fJ/conv.