Abstract
In this paper, we present methods to synthesize low power Pass Transistor Logic (PTL) cell. Given that the power consumption of a PTL cell includes power consumed at the gate terminal and source/drain capacitance when current flows from power/ground to output, we will translate finding a low power PTL cell to finding an OBDD with some defined cost function. This cost function includes the minimization of occurrence of variables with high transition probability and the minimization of the expected path length of an OBDD. To compute the cost function efficiently, three methods will be proposed to calculate the expected path length of Ordered Binary Decision Diagrams (OBDD).