Abstract
A ZrO2/Ge/ZrO2 laminate and a subsequent annealing at 600 oC was employed to formed a Ge-stabilized tetragonal ZrO2 (t-ZrO2) dielectrics with permittivity of 36.2. On Si substrate, with thin SiON as an interfacial layer, the SiON/t-ZrO2 gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. Moreover, by employing additional NH3 nitridation to passivate the leaky channels derived from grain boundaries, the leakage current achieves 4.8×10-8 A/cm2 at Vg=Vfb-1 V and the satisfactory reliability confirmed by positive bias temperature instability (PBTI) test is also obtained. An amorphous (ZrO2)x(La2O3)1-x alloy formed by deposition of a ZrO2/La2O3/ZrO2 laminate and a subsequent annealing was employed as the gate dielectric for metal-oxide-semiconductor (MOS) devices and the impact of a SiON interfacial layer on device performance was also explored. By integrating the (ZrO2)x(La2O3)1-x alloy and SiON interfacial layer as the gate stack, and the (ZrO2)x(La2O3)1-x alloy is found to have a high κ value of 28.2 with negligible amount of bulk traps, both of which are very desirable for advanced gate dielectrics. This gate stack displays good frequency dispersion in capacitance-voltage (C-V) characteristics which confirm the low interfacial trap density. In addition, MOS devices demonstrate leakage current of 2.1×10-7 A/cm2 at the gate voltage of -1 V with equivalent oxide thickness (EOT) of 1.53 nm and this performance is superior to other high-κ gate dielectrics.