Abstract
Laterally diffused metal oxide semiconductor (LDNMOS) power transistors can simultaneously act as an output stage current drive (output current driver) and an electrostatic discharge protection device. This large flexibility has been utilized in a wide range of applications such as film liquid-crystal display drivers, power management integrated circuits (ICs) and automotive (motor) electronics because LDNMOS could drive these ICs operation at high power, high voltage, high frequency, and high energy condition. Moreover, LDNMOS transistors can be downscaled to the tiny component sizes demanded of technically advanced power chip integration, facilitating the fabrication of miniature wafers with good device characteristics (on-resistance and breakdown voltage) and high device reliability. This thesis presents and evaluates the improve ESD robustness methodologies of three different structures of LDNMOS transistors from that the original configurations of the element's layout were slightly altered to enhance the electrostatic discharge (ESD) protection capability without changing the operating characteristics, increasing the device size, or adding new processing steps and extra trigger circuits. The three different kinds of LDNMOS transistors are the circular ultra-high voltage LDNMOS transistor (C-UHV NLDNMOS); isolated HV LDNMOS (ISO-HV NLDNMOS), and double reduced-surface-field HV LDNMOS (D-RESURF HV LDNMOS). Without considering the ESD protection capabilities of these LDNMOS transistors during the process development stages, they are all very vulnerable to the ESD stress. Through the detailed insight into the investigations of the failure mechanisms, the solutions how to improve the transistor ESD performances without increasing their dimensions are proposed and developed successfully. For C-UHV LDNMOS, the HBM (Human body model) failure is caused by the current crowds at the N+ junction edge of the drain. Instead of a large single N+ diffusion, these many small N+ diffusions are proposed to uniform the current distribution of the transistor by novel drain design engineering that eliminate the current crowding and enhance ESD performance is proposed. For 32V HV ISO-LDNMOS device, we find that the parasitic npn bipolar between the high-voltage N-well guard ring (HVNW-GR) and source turns on before the parasitic npn bipolar between the drain and source since it has the smaller breakdown voltage . So, the transistor fails at low-voltage ESD zapping events when the HVNW-GR is connected to the drain, while it can pass the high voltage ESD zapping events when the HVNW-GR is floated. Because the breakdown voltage of the HVNW-GR is smaller than that of the drain, the HVNW-GR can be designed as the ESD protection device (SCR) to protect the D-RESURF HV LDNMOS from ESD damaging. Therefore, for 40V HV ISO-LDNMOS device, a new low-voltage triggering silicon-controlled rectifier (SCR) was proposed and embedded in the guard rings of the LDNMOS transistor. But why it cannot be conventionally embedded in the LDNMOS transistor, the reason is that the SCR embedded at drain is not suitable for the ESD protection device design of Double RESURF HV-LDNMOS at the breakdown voltage concern. Therefore, the SCR embedded in the guard (drain) rings of the LDNMOS transistor is expected to realize next-generation small-scale devices. In summary, after slightly modified the in-situ layout by fewer mask, these modified LDNMOS successfully was enhanced the ESD robustness to meet the industry ESD specification (HBM 2kV and MM 200V) without degrading any their IV characteristic and increasing transistor size. Moreover, these improve methodologies have no additional processing steps, trigger circuits and extra area with increasing the production costs of the devices.