Abstract
For semiconductor industry, the complicated chips manufacturing process, expensive raw materials and demanding production environment make the cost relatively high. Every fabrication company eagerly searches through different manufacturing control and analysis methods to reach the goals of production cost reduction and yield improvement. In a fabrication line, the most direct and efficient way to identify an abnormal process during manufacture is by analyzing the defect maps of semiconductor wafers. Hence it is really crucial to construct a defect inspection system for semiconductor chips, which can provide better judgment and response to the detection of faults. The outcome would be an improved yield rate, the timely identification and elimination of malfunctions and eventual cost reduction.Our current research proposed a defect detection system for semiconductor wafers based on Back-Propagation Network .The major purpose of the current study is to evaluate the characteristics of defects on observed defect maps or bin maps and, thus, obtain the most related defect characteristics through the network training process. Our research will show the effect of different data conversion on the defect detection rate and provide a better output model among the various combinations of parameters. Moreover, our detection system can differentiate between the distinguishable and indistinguishable situations.Based on the verification of real-time manufacturing data provided by online engineers, it is proven that our system can correctly diagnose and analyze the defects such that it fulfills the requirements of semiconductor industry. This system could help engineers find out the problems on the fabrication line in a more timely and efficient manner so that engineers can modify the process to prevent similar problems from recurring, which would consequently stabilize the production process and even improve the yield rate.