Abstract
We propose a 12-Bit 200MS/S Current-Steering DAC based on a Segmented (5+7) current-steering architecture. In order to decrease the differential nonlinearity error (DNL) and reduce area, we employ Unary-Current cell with thermometer code decoder for the 5MSBs and Binary-Weighted Current Cell for the 7LSBs. In order to synchronize inputs and improve glitch energy, we use a digital latch approach. Differential switch order is very critical for DNL, so we use the Two Dimensional Centroid method. In order to enhance DAC output impedance and SFDR, both the MSB and LSB are implemented with Cascode Current Cell. To meet the 200MS/S and 1mm2 area spec, we perform Monte-Carlo Analysis with TSMC 0.18um Process Design Kit (PDK) and Mismatch Model. Because the Mismatch Model includes Process-Variation information, it can achieve more simulation accuracy than the corner model. Monte-Carlo simulation result, shows that when the input signal is 100MHz and sample rate is 200MHz, we have DNL=0.6LSB, and INL =0.8LSB. The chip area is 0.2mm2 in a TSMC 0.18um 1P6M CMOS Process.