Abstract
In the later stage of a VLSI design, it is quite often to modify a design implementation to accommodate a new specification, design errors, or to meet design constraints. In addition to meeting the design schedule for the new implementation, the reduction of the mask set has become very critical. In this thesis, we propose a new method which adds a programmable rectification module on a design to reduce the mask cost and to improve the turn around time. When a modification is necessary, one can program the rectification module to achieve the new implementation. The rectification module can be designed by one-mask programmable gate array, or an embedded FPGA. To reduce the size needed for the rectification module, we also propose algorithms which can intelligently select some internal signals of the old implementation as pseudo primary inputs and primary outputs. Our experimental results are very encouraging.