Abstract
The shortage of traditional IPv4 address is one of the most serious problems in the field of Internet nowadays. To solve this problem, IETF has proposed the next generation Internet Protocol, named Internet Protocol Version 6 (IPv6). However, it may take a long time to migrate from IPv4 to IPv6. As a result, we need some transition mechanisms to provide IPv6 hosts the compatibility with IPv4 hosts and routers. So far a lot of transition mechanisms have been employed, such as NAT-PT, Tunneling, and Dual Stack. In this thesis, we design and implement an IPv4/IPv6 NAT-PT translator on the Network Processor-based platform. The Network Processor is a programmable device, which is devised to process wire-speed network data. With its optimized hardware and instruction sets, the Network Processor can offer programmability, high performance, high speed, and multi-level processing. We expect that our achievement can be used as a prototype of next generation core-network equipment.