Abstract
Memory is one of the most widely used component in digital systems. Memory production test only provides failed address for repair and simple analysis. For memory design verification and yield enhancement, more detailed information such as fault type and fault location is essential. In this thesis, we will present a memory fault diagnosis system. The proposed fault diagnosis methodology is to establish a relation between fault dictionary and error syndrome. Compared to conventional approach, our system can provide more detailed information such as fault type and location using visual representation to help the engineers to improve their design and fabrication process. The proposed diagnosis system consists of the diagnostic March algorithm generator, fault simulator, and fault map generator. The diagnostic algorithm generator can provide trade-off between testing time and diagnostic coverage. The fault map generator generates the bit-map which indicates the fault type and its location. As an experiment, we have applied our system to real industry SRAM chips. According to the experimental results, about 90% of the errors are due to stuck-at faults. The address and data scrambling also has been considered. Through address remapping, we can generate the fault maps with floorplan and physical locations of the failed cells.