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以鎵自催化方式在矽基板上所成長的核殼結構砷化鎵奈米線與其電性質
Thesis

以鎵自催化方式在矽基板上所成長的核殼結構砷化鎵奈米線與其電性質

古又中
Masters, 國立清華大學, 材料科學工程學系
2013

Abstract

砷化鎵 分子束磊晶 Ⅲ-Ⅴ半導體 奈米線 GaAs MBE Ⅲ-Ⅴ semiconductor nanowires
To data, GaAs nanowires(NWs) have been mostly grown on the GaAs substrates, while, far fewer studies have been on the synthesis of GaAs NWs on Si substrates by molecular beam epitaxy (MBE). The growth of GaAs NWs on Si offers the possibility to investigate the optical and electrical properties of the nanowires; moreover, it is expected to combine advantages high efficient III-V materials and low-cost silicon technology. Traditionally, fabrication of GaAs NWs has mainly relied on the use of gold as catalyst via the vapor-liquid-solid (VLS) mechanism. However, the incorporation of gold may generate deep level traps and degrade the electron and hole transport properties of the nanowires. In this work, so-called self-assisted method was employed to grow the GaAs NWs on (1 1 1)Si, where Ga droplets in the pinholes of Si native oxide were used to induce anisotropic growth. We have successfully grown coaxial GaAs NWs on Si(111) substrates by MBE using Be and Si as the p-type and n-type dopants, respectively. During NW growth, we fixed the shell growth time and changed the core growth time. We found the lengths of the nanowires increase with core growth time, while the diameters of the nanowires remain almost constant. All the GaAs core-shell NWs have been subjected to the following pn junction fabrication processes: insulator spin coating, insulator reactive-ion-etching, and conductive layer depositing. I-V properties of the as-fabricated nanowire pn devices were then investigated. We discussed the effect of the nanowire length, insulator etching condition, and types of conductive layer on the I-V properties of NW devices. We observed all fabricated NW devices have exhibited the properties of diode, suggesting their potential use as building blocks in solar cells.

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