Abstract
In this thesis, we present a pipelined bit-serial VLSIarchitecture for realizing an N-tap adaptive FIR filter usingthe delayed least mean square (DLMS) algorithm. Thearchitecture consists of bit-serial systolic arraysfor performing filtering/adaptation operations and a memoryscheme for arranging input data flow. It possesses low-powercharacteristics and is suitable for single-chip VLSIimplementation. The efficiency of the system is 100 percentand the throughput is one filter output per 2B cycles, whereB is the word length of input data. Moreover, theproposed approach uses a small delay in the filtercoefficient adaptation, and this ensures that the DLMSalgorithm can have good performance under proper selectionof the step size. As compared to a related bit-serialapproach described previously, the proposed one has reductionin both chip area and power consumption.