Abstract
Reducing power consumption is a crucial challenge to system designers. Portable systems, such as laptop computers and handheld devices, draw power from batteries, so reducing power consumption prolongs battery life. In this thesis, we promote two software techniques for power reduction: the compiler and the operation system solutions. In the compiler approach, a data-flow analysis framework which estimates the component activities at fixed points of programs with the consideration of pipelines of architectures is proposed to reduce leakage power consumption of useless components. As the duration of power gating on components on given program routines is related to program branches, three scheduling mechanisms for power-gating instructions, called Basic_Blk_Sched, MIN_Path_Sched, and AVG_Path_Sched, are presented and discussed. In addition, we describe a prototype implementation of our approach in SUIF and MachSUIF, a compiler system, to validate the effectiveness. We build the experimental architecture, which is compatible with the DEC Alpha 21264 processor and employs power gating mechanism, within the Wattch simulation environment. The experiments show that our approach reduces average 82% of power consumption for floating-point units and average 9.9% for total power consumption against the clock gating mechanism. In the operating system approach, we focus the issue on scheduling problems for variable voltage processors in real-time systems. A reservation list scheduling algorithm based on the well-known EDF (Earliest Deadline First) and six decision algorithms which help to decide the voltage of processors are proposed. Also, simulation results of our scheduling polices on a CNC (Computerized Numberical Control) machine controller, a task set, are presented. The simulation results show that our variable voltage scheduling policies is about 62% power reduction against the fixed voltage systems.