Abstract
The market of mobile wireless devices has rapidly expanded and that are being used increasingly around the life everywhere. To achieve wireless connectivity for inexpensive or disposable devices, low cost wireless arcitectures and transceiver. In this thesis we will study the fundamentals and possible architectures of RF Front-End. Hopefully they can be applied for integrated low power, low cost wireless applications. This thesis contains two parts. In first part, the RF performance of CMOS circuit under low current dissipation (below 1 mA) is study. A common gate single-balanced Gilbert Cell mixer is chosen as a test circuit. The theoretical operation of the circuit is introduced and modeled by equations. The analytical predictions then be verified by Cadence SpectreRF simulator. Good agreements between the predictions and experimental data are obtained. In second part, we tried to construct a low power RF Front-End. Rather than the published CMOS receivers that will dissipate a power from 50 to 200 mW, in this work an 4.3 mW ultra-low power, 2.4G Hz high frequency, 1060 um x 863 um small chip size RF front-end of dual conversion architecture is proposed. The front-end using 0.18 um standard CMOS process achieves 9.2 dB noise figure at 200 kHz with -22 dBm IIP3 under a 1.8 V supply. The image rejection ratio is expected to be 136 dB.