Abstract
The objectives of this thesis is to explore in depth the feasibility of low-voltage, high-speed Floating-Gate (FG) Flash memory cell through the proper minimizations of tunneling oxide and inter-poly dielectric (IPD) layers. Here, high-k materials and metal control gate are adopted in stacked gate to promote the control gate coupling ratio. Detailed investigations of device parameters in FG Flash cells are performed with two-dimensional device simulations and real silicon fabrications to attain the possible high-speed and low-power Flash cell design.