Abstract
As the CMOS technology develops, the number of buffers required in a network-on-chip increases with flit width. This increase of buffers provides more power and area overhead to a network router. This thesis proposes a hybrid packet-switched and circuit-switched network in which the total buffer requirement depends on only the width of the short message and buffer depth, and does not increase with the network width. The performance is maintained through a low latency circuit-switch by using a simple reverse path reservation method.The simulation results indicated that, the proposed network costs 56% of power consumption and 52% of area overhead, accompanied by 1.1% of performance improvement compared with the baseline network under the 128-bit network width configuration. And the power consumption and area overhead of proposed network reduce to 32% and 40%, respectively, while exhibiting 1.4% performance improvement compared with the baseline network under the 256-bit network width con-figuration.