Abstract
In this work, we propose a new self-aligned process that integrates CNT via and pre-existing cobalt tungsten phosphide (CoWP) metal barrier at the via bottom as a catalyst for future CMOS interconnect applications. The CoWP is an effective Cu diffusion barrier, which is anticipated to be used in real devices in 2006 according to ITRS roadmap. Moreover, CNT has extremely high current density capability (Jmax > 109 A/cm2), thermal conductivity, thermal stability, and mechanical strength, which make it a very promising material for future interconnect. The focus of this work is to grow low-resistance and high-density CNTs into fine-feature and high aspect ratio via holes at 400 ℃ utilizing CoWP as the catalyst. The first challenge is to grow CNTs at 400 ℃, which is the requirement of IC back-end process. The second challenge is to synthesize CNTs using CoWP as a catalyst, which has never been done before. Experimental results showed that CNTs with a density of 9.23x1010 /cm2 were successfully grown on CoWP thin film after series of process optimization. We further grew CNTs with a density of about 1.3x1011 cm-2 in Cu dual damascene structure with a via size of only 100 nm. The I-V curve of these CNT vias show ohmic characteristics with an average via resistance of 13.5 kΩ/via. These results demonstrated the feasibility of this simplified self-aligned process for future CMOS interconnect by integrating CoWP barrier and CNT via to greatly reduce the process complexity and improve the device performance.