Abstract
The scaling trend of flash device is limited by the dimension of planar device, which makes the process flow more complex. How to improve the operational characteristics and increase the device density at the same time become two of the most important issues. Some approaches have been reported such as high-k material, nanowire channel structure, junctionless (JL) channel and 3D array flash memory devices. In this thesis, a low temperature formed SiO2 is proposed as tunneling layer for nano-wire and stacked vertical gate structure charge trapping (CT) flash memory devices. The purposes are to reduce thermal budget and increase device density. In the first study, a low temperature formed SiO2 is proposed to replace conventional high temperature SiO2 as tunneling layer. HfO2/Si3N4 stacked trapping layers are implemented to improve the operational characteristics of nano-wire inversion mode flash device. It is found that operational characteristics such as program/erase (P/E) speed、retention and endurance characteristics of low temperature formed SiO2 are as good as those with high temperature formed SiO2. HfO2/Si3N4 stacked trapping layers device has better P/E speed and good reliability characteristics truely. In the second study, a low temperature formed SiO2 is used as tunneling layer and HfO2/Si3N4 stacked trapping layers to improve the operational characteristics of nano-wire junctionless device. It is found that HfO2/Si3N4 stacked trapping layers device has good P/E speed、memory window and reliability characteristics. Therefore, low temperature formed SiO2 is promising to be applied to 3-D stacked device. In the last study, low temperature formed SiO2 is applied to stacked vertical gate structure. Effect of HfO2/Si3N4 stacked trapping layers on operational characteristics of the stacked vertical gate device is also studied. It is found that HfO2/Si3N4 stacked trapping layers device improves its P/E speed、retention and endrance characteristics truly. However, the reliability characteristics of all devices are not good enough. Therefore, improvement of ICPCVD formed SiO2 is necessary on such a stacked vertical gate structure.