Abstract
The scale down of flash device is limited by its micro-miniature planar devices, which makes the process flow more complex. How to improve the electrical characteristics and increase the device density at the same time becomes two of the most important issues. Some approaches have been reported such as the BE-SONOS, nanowire channel structure, junctionless (JL) channel and 3D array flash memory devices. In this thesis, a 3D stacked structure is implemented in charge trapping (CT) flash memory devices with high-k stacks to increase device density. Besides, the performance can be improved by HfO2/Si3N4 stacked trapping layers. In the first study, a CT flash device with stackable vertical gate structure is demonstrated for 3D memory integration. It is found that the program/erase (P/E) speeds and reliability of top and bottom devices are similar. Small program disturb and large disturb-free window are achieved. However, a conventional SONOS dielectric layer is used on JL channel flash memory devices. The erasing speed is still an issue and it need to be improved. In the second study, the HfO2/Si3N4 stacked trapping layers are implemented on the same vertical gate structure as the first study. We want to know if the stacked trapping layers can improve the erasing performance on this device. The results show that the devices exhibit better programming speed and reliability. Besides, erasing speed becomes faster by using bandgap engineering trapping layers. In the last study, although HfO2/Si3N4 stacked trapping layer plays an important role on flash memory, its thermal cycle in fabrication process may induce the degradation of trapping layers in 3D structure devices. To reduce thermal cycle, a low-temperature formed Si3N4 is used to replace the conventional one. The low-temperature formed Si3N4 is deposited by inductively coupled plasma chemical vapor deposition (ICPCVD), and a high-temperature formed one is conventionally deposited by a low pressure chemical vapor deposition (LPCVD). From the energy-dispersive spectroscopy, the compositions of Si3N4 layers are different, result in that P/E speed of ICP sample is faster than that of LPCVD one. Besides, LPCVD sample has better retention than ICP one.