Abstract
The performance level and reliability of low temperature polycrystalline silicon thin-film transistors (LTPS TFTs) have greatly improve in recent years as a result of intensive research for the integration of high speed circuits on glass substrates (SOP). With their high mobility and operation stability, LTPS-TFTs have been used extensively in small-to-medium display panels. In display applications, LTPS TFTs are exposed to fairly strong backlight from the back plane and/or ambient light. Under illumination, photon-induced carrier generation on the poly-Si body can induce large off-state leakage current, much higher than that in a dark environment. High off-state leakage current in these TFTs not only lead to increased standby power, but also cause operation errors as well as degradations in display quality. The introduction of a bottom shielding gate is expected to eliminate photo-induced leakage effectively. However, the subsequent additional drain turn-on effect can become problematic for the TFT driving circuits. In this study, we investigate the design of the bottom shielding gate to optimize the off-state drain leakage current suppression as well as minimizing the drain turn-on effect. Asymmetric shielding gates and surround structures are found to be a promising solution to alleviate the drain turn-on problem. Dual and double gate designs are also effective and reliable methods to minimize the off-state photo leakage current without enhancing the drain turn on effect.