Abstract
In this thesis, a row share strategy, that combined factor share and distributed arithmetic are proposed to build low-cost DCT (Discrete Cosine Transform) and IDCT (Inverse Discrete Cosine Transform) transforms. The proposed architecture can support multi-standard transform, such as MPEG-4, H.264, and VC-1 including 8 x 8、8 x 4、4 x 8 and 4 x 4 transforms. Besides, based on the similarities of DCT and IDCT transforms, we reuse the same circuits to manipulate DCT and IDCT by interlaced sorting methods. Not only the cost of area is saved, but 1D DCT(IDCT) and 2D DCT(IDCT) are also operated continuously to reach the high throughput rate and meet the demands of real-time system. A new parallel structure core circuit is proposed to have the advantages of high-throughput rate and low-cost area compared with previous works. The proposed core requires 68 cycles in latency for 128 data consisted of 2 8x8 blocks. The proposed design uses a TSMC 0.18-um 1P6M CMOS process to implement this chip. In simulation, the operating frequency is 125MHz in slow model and achieves 500MHz throughput rate with 39.5K gate counts. The proposed core can support HDTV(1920 x 1080P@60Hz) in real-time video encoder.