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作為測試研究目的之DLX架構下的ARM指令集處理器
Thesis

作為測試研究目的之DLX架構下的ARM指令集處理器

吳建宏
Masters, National Tsing Hua University
2000

Abstract

處理器測試指令集 ProcessorTestingInstruction SetDLXARM
An embedded processor based on the DLX architecture is introduced in this thesis. It is designed with the capability of performing ARM instruction set and is also supported by these toolkits, which are developed for the ARM. We name the processor as "DLX based Arm instruction set Processor" (DAP). Depending on the features of both DLX and ARM architecture, the DAP invokes the load-store architecture, fixed legth instruction set, pipeline capability, conditional execution and exceptions. Due to the difficulty of testing of embedded modules deeply in processor core, we also refer to a testing methodology for the proposed processor to ensure our design functionality. The application of this processor is mainly focused on testing in SOC design.

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