Abstract
In recent years, digital signal processing (DSP) processors which use in many of the wireless communication systems has been requested high-performance. In this thesis, we propose the high-performance and low-cost design for Computation Sharing Programmable FIR Filter. Today, there are three kinds of methods for FIR filters design. There are common subexpression sharing/elimination method [3], [4], adder graph approach method [7], [8] and difference method [6], [11]. The most commonly used is common sub- expression sharing/elimination. The idea here is to find common patterns in the representation of the multiplier coefficients. This means that the mul- tiplier partial products can be shared. We use this concept to bring up Computation Sharing Programmable FIR Filter and then we base on this architecture to improve it. The Computation Sharing Programmable FIR Filter can replace many of the FIR Filters which is used in the DSP system for different communication specifications, and it can achieve DSP system to high efficiency. In the article, we mentioned a Computation Sharing Multiplier (CSHM) which used Canonic-Signed-Digit (CSD) representation in FIR Filter design can make high performance and low complexity in application. Beside, we improve the Programmable FIR Filter for different Pre-computer bit word lengths and give simulation analysis to validate theories. Finally, we discuss the design what are the difference about the Computation Sharing Programmable FIR Filter and use CSD representation to improve it. Finally, we discuss the difference about area, power, and timing between Computation Sharing Programmable FIR Filter using CSD representation and non-use of CSD representation.