Abstract
The Advanced Encryption Standard (AES) algorithm is a new standard of symmetric-key crypto system. The algorithm was announced by the National Institute of Standards and Technology (NIST) of the United States in 2001 in order to replace the Data Encryption Standard (DES) algorithm. In recent years, many hardware implementations have been proposed. Most of these hardware designs focused on the S-Box, and implemented the key scheduler by the memory based method. We propose an efficient hardware implementation of the AES algorithm using on-the-fly key scheduling method. Different from the method of the memory based key scheduler, the proposed method reduces the power dissipation and is suitable for integration into the system chips. We also modify the round function to shorten the path delay and reduce the hardware complexity, i.e., there are 2 MUXes and 5 XOR gates for encryption or 2 MUXes and 8 XOR gates for decryption saved in the critical path. Also, the Electronic Code Block mode (ECB), Cipher Block Chaining mode (CBC), and Counter mode (CTR) operating modes are supported in our design. Using a typical 0.18¹m CMOS technology, a 125MHz clock rate is achieved, and the throughput rate is 1.6Gbps for 128-bit key, 1.33Gbps for 192-bit key, and 1.13Gbps for 256-bit key, respectively. Moreover, power and testability issue of the design are also considered. We apply standard low-power design methods to reduce power, and the power consumption of the AES chip is about 56mW in the worst case. In addition, the fault coverage is about 99.93% and the gate count is about 67.9K in the design.