Abstract
As the manufacturing technology progresses to deep sub-micron nodes, people must make more efforts to keep better clock signal in digital integrated circuit design than ever. Asynchronous circuits directly remove the clock signal, and make circuit operate more efficiently. In this thesis, we developed an asynchronous design implementation approach which adopts commercial computer aided design tools and synchronous cell libraries, in an attempt to remove the deficiency and restrictions in current asynchronous design flows. Most of current asynchronous design flows are different with synchronous standard flows. They need the support of additional cell libraries, and designers be reeducated for unfamiliar programming language and tools. The proposed asynchronous implementation approach is based on globally asynchronous locally synchronous (GALS) system. All the building blocks are separated and allow individual improvement and modifications. As a result of our research, we found that current synthesis tools are not suitable for asynchronous circuits, and thus we pointed the shortcomings of synchronous synthesis tools as applying to asynchronous designs. We hope that synthesis tools can be improved for the use of asynchronous IC design in the future. To measure the performance of the proposed asynchronous circuits, we analyzed the timing in single-stage and multiple-stage pipeline configurations, and pointed the phenomenon of blocking and starvation due to data dependency in multiple-stage circuits. At the end of thesis, full comparisons of synchronous and asynchronous designs in performance, area, energy, and modularity are carried out.