Abstract
With the improvement of VLSI technology, dimensions of BEoL (Back End of the Line) interconnect becomes smaller and smaller. For most circuit designers, they want to put more transistors on the smaller die size. Thus, interconnect will be complicated and scale down. There are more interconnect-induced effects which need to be considered in advanced technology when the process scales down. IC designers need an accurate BEoL corner model to help their circuit design. In this paper, we design a test structure generator. Inside the generator, there are several P-cells for different purposes. They are embedded test structures of the generator. Users can generate the test structures by their requests. It can customize the requests from users. Users only spend a short time and they can get their test structures. It focuses on generating the test structures for VLSI BEoL. After the generation of the test structures, there is still a step for debug. This step can find most connectivity errors. Using these structures to measure all electronic data can derive to get SIPPs, which are the parameters for VLSI BEoL corner model.