Abstract
In [1], Wong and Liu proposed a slicing structure to represent a floorplan topology with the corresponding Polish expression. It can not process non-slicing structure, but non-slicing structure actually derive an efficient utilization on area. H. Murata et al [2,3] propose a new topology representation, called sequence-pair, to overcome this drawback. We propose a floorplanner with minimization of core area and inter-block wire length supporting based on sequence-pair. Solution space is searched by simulated annealing algorithm (SA) and genetic algorithm (GA). Experimental results show that the floorplan layout of SA is better than that of GA in sequence-pair representation, but GA can generate a good solution quickly in early few iteration and then reduce the execution time.