Abstract
This paper describes the design of using time amplification in time-to-digital converter (TDC) with two level vernier delay line (VDL), which is used to solve the limitations of chip area, power consumption, and device mismatching of VDL in 10 picoseconds or less time resolution. In this paper, we proposed a new TA architecture based on differential difference amplifier (DDA) in unity gain buffer configuration. The gain is adjustable between 2 to 20, which can be controlled by the output common-mode voltage of DDA, and the input range can up to about 60ps. The proposed TA is applied to a 9-bit two-stage TDC. The TDC is using a two-stage VDL structure. The first stage has five bits, and the second stage has four bits. The TA with a gain of 16 is placed in between the two VDLs. After the five most significant bits (MSB) time-to-digital conversion is first carried out by the coarse VDL, the time residual of the coarse VDL is transferred to the TA through an interface circuit. The fine VDL then converts the amplified time residual to the four least significant bits (LSB). Both VDLs have designed with the same timing resolution of about 40ps, which is the intrinsic delay of inverters. A 9-bit two-stage vernier delay line time-to-digital converter has been proposed using TSMC 0.18um CMOS process. Simulation result shows that the overall time resolution of the TDC is 3ps, and the full input range is about 1.44ns. Besides, the DNL and INL are -0.5~0.9 LSB and -0.8~1 LSB, respectively.