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使用氧化鉿及氧化鈰薄膜之電容器與場效電晶體的電性與可靠性分析
Thesis

使用氧化鉿及氧化鈰薄膜之電容器與場效電晶體的電性與可靠性分析

陳俊衡
Masters, National Tsing Hua University
2006

Abstract

高介電常數薄膜氧化鉿氧化鈰崩潰電荷缺陷密度閘控二極體介面捕陷密度等效捕陷截面積
Metal-insulator-semiconductor (MIS) capacitors and n-channel field effect transistors with HfO2 and CeO2 gate dielectrics were successfully fabricated. The reliability properties such as charge-to-breakdown (QBD) with different types of current stress were characterized. The high-k/Si interface properties with CeO2 and HfO2/CeO2 laminated gate oxides were investigated by the gated-diode technique. The Weibull slope and the defect size of HfO2 gate dielectric were determined. The extracted Weibull slope (β) from constant current stress (CCS) measurement for different thicknesses of 9.12 nm, 8.2 nm and 6.51 nm are found to be 3.42, 2.90 and 1.83, respectively. The defect size a0 extracted by the cell-based analytic model with different exponents of 0.6 and 1 are 0.97 nm and 1.63 nm, respectively. The extracted Weibull slope (β) from transmission line pulsing (TLP) measurement for thickness of 9.12 nm is about 3.86. The QBD values extracted from the TLP method are about 5 order of magnitude smaller than those extracted from the CCS method. However, the hole generation coefficient extracted from the TLP method is about 4 order of magnitude larger than that extracted from the CCS method. Hence, this can quantitatively explain the difference of QBD between the CCS method and the TLP method. The interface trap density (D?it) of CeO2 and HfO2/CeO2 laminated gate dielectrics determined by the subthreshold swing method are 1.47×1012 cm-2 eV-1 and 1.53×1012 cm-2 eV-1, respectively. The effective capture cross section of surface state (σs) of CeO2 and HfO2/CeO2 laminated gate oxides extracted using the gated diode technique and the subthreshold swing measurement were about 8.68×10-15 cm2 and 4.83×10-15 cm2, respectively.

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