Abstract
In the present work, we propose the idea of using vernier ring delay line (VDL) with to develop a 13 bit two stage time to digital converter. The converter is based on the fundamental method of counting the full clock cycles of a low-phase-noise reference clock. The use of vernier ring delay line technique significantly relaxes the device matching requirement than vernier delay line (VDL) and also reduces the chip area. Simulation results showed that the time resolution is around 12.44ps and the full input range is about is 44.8ns. The present work is designed using 0.18um CMOS process. Simulation result shows that the overall time resolution of the TDC is 12.44ps,the full input range is about 44.8ns. Besides,respectively.