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使用統計學的方法分析電路的可測試性
Thesis

使用統計學的方法分析電路的可測試性

邱創祺
Masters, 國立清華大學, 資訊工程學系
2006

Abstract

測試 testing
This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulation governed by the formulated Monte Carlo model. The Monte Carlo simulation is terminated when the predefined error with respect to the Monte Carlo model, under a specified confidence level, is achieved. We conduct the experiments on a set of ISCAS'85 and MCNC benchmarks. As compared with previous work, our approach more efficiently evaluates the testability with less error.

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