Abstract
Research directions in reducing power consumptions have recently begun to address the issues of arranging softwares at instruction-level to help reduce power consumptions. In this thesis, we present studies in the compiler participation to reduce power consumptions by incorporating power consumption models into the compiler and code-generations. Our investigations include two aspects. First, we address the power consumption issues on the instruction bus. We give a thorough investigation on the compiler transformation techniques to the problem of scheduling VLIW instructions aimed to reduce the power consumption of VLIW architectures in the instruction bus.The problem can be categorized into two types: horizontal scheduling and vertical scheduling. For the case of horizontal scheduling, we propose a bipartite-matching scheme for instruction scheduling. We prove that our greedybipartite-matching scheme always gives the optimal switching activities of instruction bus for given VLIW instruction scheduling policies. For the case of vertical scheduling, we prove that the problem is NP-hard, and we further propose a heuristic algorithm to solve the problem. Second, we propose aprofiling scheme to reduce the power consumption of Booth multipliers by arranging operands of the multiplier instructions. The scheme is useful for embedded applications and ASIC environments. Our profiling scheme can optimizethe power consumptions of Booth multipliers on both the transition activity on its latches and the action of Booth multiplier (according Booth recoding's behavior.Our experiment is performed on Alpha-based VLIW architectures and ATOM simulator, and our compiler incorporated by our proposed schemes is implemented based on SUIF and MachSUIF. We report experimental results for booth multipliersand for instruction bus. In the case of the instruction bus, experimental results show average 13% improvements with 4-way issue architecture and average 20% improvement with 8-way issue architecture for power consumptions of instruction bus as compared with conventional list scheduling for an extensiveset of benchmarks.