Abstract
This paper describes the design of time-to-digital converter with two level Vernier delay line（VDL）, which is used to solve the problem of long conversion time in single level VDL and reduce the elements. The time to be measured between two pulse signals is separated into integral period part and non-integral period parts by control circuit. Integral part is sent into counter, and non-integral parts are sent into the two level VDL. In the first VDL can get coarse resolution（Tclk/14）, and the signals will be transferred to the second VDL by the new structure interface circuit. Fine resolution（Tclk/196）can be gotten in the second VDL. Finally, readout circuit converts thermal code to binary code and do the subtraction to get the final results. The bias voltages of delay elements in VDL are controlled by DLL, this makes delay elements can stably provide two delay time：Tclk / 14 and Tclk．15 / 196. The circuit uses the process of TSMC CMOS 0.18um 1P6M. 200Mhz clock frequency is chosen by the consideration of delay time, conversion time, and error analysis. From the simulation results, the conversion time is smaller than 5 clock periods, the maximum time can be measured is 75ns. After the fine resolution is modified to 29.6ps, the DNL is within -0.33LSB ~ +0.69LSB，and INL is within +0.47LSB ~ +1.08LSB.