Abstract
In this thesis, we propose a digital-to-time converter (DTC) system with two phase-locked loops and impulse window generator (IWG). Among the DTC system, the output signal of the first stage PLL is 100MHz with 75 selections of phase, the time resolution is 133.33 ps. Owing to the structure of two stage cascade PLL, the output signal of the second stage PLL is 100MHz with 5700 selections of phase, the time resolution is 1.754 ps. Furthermore, by the last stage IWG processing, the system has the 12.5 MHz impulse signal with 1.754 ps time resolution, applicated to the impulse radar. The impulse radar transmits impulses with period 80 ns and pulse width 1.05 ns. At the VCO output of the second stage of PLL, the carrier wave 7.6 GHz is turned on by the impulse signal control. By multi-stage of delay shift register (DSR), clock signals can be phase shifting and phase rotation in high time resolution. However, the first stage DFF in the delay shift register have metastability issues, if the data input D doesn’t have enough setup time and hold time. This situation give rise to the failure of phase shifting operation. Therefore, we insert the programmable delay line circuit in front of DFF input D, particularly calibrated the time delay prevent form metastability. The system is implemented in TSMC 0.65 nm 1P9M CMOS process, the output of impulse signal have 15.48-bit (45600) selections of phase.